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战斗力 鹅
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注册时间 2011-11-4
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本帖最后由 hidebumi 于 2015-10-14 13:58 编辑
都说tlc不好,那为啥850evo保5年呢
https://en.wikipedia.org/wiki/Charge_trap_flash
In a charge trapping flash electrons are stored in a trapping layer just as they are stored in the floating gate in a standard flash memory, EEPROM, or EPROM. The key difference is that the charge trapping layer is an insulator, while the floating gate is a conductor.
High write loads in a flash memory cause stress on the tunnel oxide layer creating small disruptions in the crystal lattice called “oxide defects.” If a large number of such disruptions are created a short circuit develops between the floating gate and the transistor’s channel and the floating gate can no longer hold a charge. This is the root cause of flash wear-out (see Flash memory#Memory wear), which is specified as the chip’s “endurance.” In order to reduce the occurrence of such short circuits, floating gate flash is manufactured using a thick tunnel oxide (~100Å), but this slows erase when Fowler-Nordheim tunneling is used and forces the design to use a higher tunneling voltage, which puts new burdens on other parts of the chip.
A charge trapping cell is relatively immune to such difficulties, since the charge trapping layer is an insulator.[5] A short circuit created by an oxide defect between the charge trapping layer and the channel will drain off only the electrons in immediate contact with the short, leaving the other electrons in place to continue to control the threshold voltage of the transistor. Since short circuits are less of a concern, a thinner tunnel oxide layer can be used (50-70Å) increasing the trapping layer’s coupling to the channel and leading to a faster program speed (with localized trapped charges) and erasing with lower tunneling voltages. The lower tunneling voltages, in turn, place less stress on the tunnel oxide layer, leading to fewer lattice disruptions.
Another important benefit of using a charge trapping cell is that the thin charge trapping layer reduces capacitive coupling between nei**oring cells to improve performance and scalability.[6]
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